The present invention relates to a processor of a video signal which receives a video signal for display from a computer or the like, performs various processing and displays these processed signals on a display unit.
A video signal for display outputted from an engineering work station, a personal computer or a display terminal of a computer or the like has been heretofore outputted as an analog signal in the unit of dot corresponding to a pixel on a display scope. It is possible to perform various processing such as conversion of a signal format such as a field frequency and an aspect ratio and picture processing such as enlargement and reduction, picture synthesis and geometric conversion by converting the video signal into a digital signal and using a memory or an arithmetic processing circuit. For example, when a four-side multiscreen system in which four units of displays are arranged in two stages longitudinally and two units adjacent to each other horizontally and display is made supposing these displays as one set of display is formed, a quarter signal of the input video signal is enlarged all over the scope, and displayed on a display unit positioned at a corresponding position. With this, a large-sized display system of high brightness and high resolution having a comparatively small installation area such as depth can be constituted.
A basic structure of a signal processing circuit for performing digital signal processing is shown in FIG. 1. An input video signal SI is converted into digital data by means of an Analog to Digital (A/D) converter 101 and written in a memory 102. Such memory write processing is performed by the control of a write control circuit 105 with a synchronizing signal of an input video as a reference. The video data written in the memory 102 are read out by a control signal of a read control circuit 106, and are converted into an analog signal again by means of a Digital to Analog (D/A) converter 103 and outputted. It is possible to perform various picture processing such as enlargement and reduction of the picture size and conversion of the field or frame frequency by controlling an address to a memory or differentiating read/write clock frequency during the process of write in and read out of the memory.
As to synchronization of an output video signal at this time, there are a method of generating the video signal from a clock produced by a crystal oscillator or the like irrespective of an input video signal, and a method of generating the video signal from a synchronizing signal of an input video and so on, which are selected in accordance with the system.
In a multiscreen system for displaying by using a plurality of display units and so on, it is required to display while setting output synchronization phases one to another in order to true up display timings of adjacent video signals. Since a horizontal scanning speed is sufficiently fast in general as compared with afterimage characteristics of human beings, perfect phase synchronization is not required, but it is required to have the vertical frequency of slow scanning speed synchronized. In particular, when vertical frequencies of display in the upper and lower stages are not synchronous with each other, flickers (line crawling between stages) due to discontinuity of vertical scanning are generated in the vicinity of the connecting portion from the upper stage to the lower stage, thus causing noticeable picture quality deterioration.
Further, it is required to have vertical blanking periods coincide with one another and to change over a signal during this period also for displaying a plurality of video outputs while switching them in an instant without discontinuity of videos.
When a single signal is inputted while branching it off in a plurality of signal processing circuits and displayed at the same time, it is sufficient to form a structure for generating synchronization of output video signals from a synchronizing signal of the input video by a PLL or the like. Since synchronization of the output video signals is generated from the same input signal, it is possible to have them synchronize in phase mutually. In this method, however, video signals outputted from a plurality of independent computers or image terminals are not synchronous in phase with one another even in the case of the video signal has the same image format such as a horizontal scanning frequency and a line number. Therefore, it is impossible to set the synchronization on the side of the processor.
In a conventional apparatus, a Generation/Generator Lock: Gen Lock system in which horizontal and vertical synchronizing signals which become the reference are inputted from external synchronizing input terminals 110 and 111 and a video signal is outputted with these signals as the reference is used as a method of solving the above-mentioned problem. Since a video signal synchronous in phase with both the horizontal and vertical synchronizing signals inputted from the outside in this Gen Lock system, it is possible to synchronize a plurality of video signals with one another irrespective of the phase of the input signal.
In a conventional Gen Lock system, however, the output format such as horizontal and vertical scanning frequencies of the output video signal has to coincide with that of the external synchronizing signal inputted as a reference signal. Therefore, when the output format from the signal processing circuit is altered, it has been required to change the format of the reference signal from the outside at the same time.
Further, when it is intended to output a plurality of signals of different formats at the same time with synchronization, reference signal sources with the outputs synchronized become necessary by the number of formats that are being displayed at the same time. Furthermore, it has been also required to switch these signal sources appropriately or to connect them over again.
Further, a method that attention is paid only to the vertical synchronizing signal for a Gen Lock reference signal source from the outside and the vertical synchronizing signal from the video signal processor, and both are compared with respect to phases, and the oscillation frequency of a read clock is controlled by a Phase Locked Loop (PLL) is conceivable. In this method, however, control is made by phase comparison of vertical frequency of 20 to 120 Hz. Therefore, there has been such problems that the response speed of the loop cannot be made fast, and the operation is liable to become unstable because of a leakage current, a disturbance factor and so on of a capacitor of a loop filter.